1. Field of the Invention
The present invention relates to an output buffer and an output buffering method, and more particularly, to an output buffer which can be used for an integrated circuit.
2. Description of the Related Art
Conventional output buffers have been disclosed in many texts. For example, a conventional output buffer is shown in FIGS. 5-61 on pages 229-230 in a text which was written by Neil Weste and Kamran Eshraghian and published with a title "Principles of CMOS VLSI design" and a subtitle--A systems perspective--in 1985 by the Addison Wesley publishing company.
FIG. 1 shows a conventional output buffer comprised of an output buffer 10 and an output port 20. The output buffer 10 is comprised of an inverter 12, a NAND gate 14, a NOR gate 16, and PMOS and NMOS transistors MP0 and MN0.
The output buffer 10 of FIG. 1, which is used for an integrated circuit, delays input data DA having a logic "high" or "low" level for a predetermined period of time and provides the delayed data to the output port 20. The output buffer 10 is built in the integrated circuit. Generally, the output buffer 10 is enabled in response to an output enable signal OEB having a logic "low" level. When the input data DA is a logic "high" level, the output buffer 10 applies a source current to a load capacitor (not shown) included in the output port 20 using a pull-up transistor MP0 and thus charges the load capacitor with the source current, thereby increasing the potential of the output port 20. When the input data DA is a logic "low" level, the output buffer 10 sinks the current charged into the load capacitor (not shown) of the output port 20 using a pull-down transistor MN0, thereby discharging the capacitor and lowering the voltage of the signal output from the output port 20.
In the circuit of FIG. 1, in order to sufficiently drive a load (not shown) connected to the output port 20, a relatively large amount of current must flow in the pull-up and pull-down transistors MP0 and MN0 of the output buffer 10, as compared to other circuits within a system that uses the output buffer 10. When such a current passes through the bonding wire and the lead frame of a power supply V.sub.DD and a ground V.sub.SS pin, an induced electromotive force [V(t)] expressed by the following Equation 1 is generated: ##EQU2##
wherein L denotes inductance and i denotes the current supplied to a load (not shown) connected to the output port 20. Here, the induced electromotive force causes the ground voltage (or a reference voltage ) V.sub.SS to bounce. That is, the conventional output buffer 10 has a problem in that a ground bounce effect is caused by the induced electromotive force. Furthermore, as can be seen from Equation 1, ground bounce becomes more serious with an increase in the total amount of inductance or in the variation of current according to time.
Due to the development of semiconductor manufacturing techniques and increases in the operational speed of systems including semiconductors, the size of a load (not shown) to be driven by the single output buffer 10 increases, and the driving speed becomes faster. Hence, the noise and distortion in a buffered signal OUT are increased due to the ground bounce effect and an impedance mismatch between the output port 20 and the output buffer 10.